Typically, a two-bit SONOS (silicon-oxide-nitride-oxide-silicon) memory device is programmed by using channel hot electron injection, i.e. by injecting the electrons from the channel into a region of the silicon nitride layer near the source or near the drain. Since the electrons can be trapped locally at two opposite sides of the silicon nitride layer near the source and the drain, two bits per cell can be accomplished.
Further, multi bits per cell can be achieved by using multi-level cell (MLC) technique, which enables the memory cell to have multiple threshold voltages by storing different numbers of electrons into the floating gate. The state of the memory cell can be determined by applying a reading voltage between two of the multiple threshold voltages and then reading the corresponding current.
However, for these conventional multi-level cells, the voltage difference between the threshold voltages should be large enough to avoid erroneous determinations. Furthermore, the number of the electrons injected into the floating gate should be relatively precise, which results in complex operations and inferior reliability and endurance.
Consequently, it is necessary to provide an operation method of memory device capable of reducing erroneous detection and providing a wider range of reading voltages.